Even as the high performance computing community approaches 100 Teraflops Linpack performance, challenges to supercomputer hardware and software design may impede further progress and limit scalability, performance to cost, generality, reliability, and programmability. The consequence of these factors may be reduced impact of supercomputing on science, technology, industry, commerce, national security, and society even as its capability approaches important new levels. While commodity microprocessor and DRAM based clusters and MPPs have dramatically advanced the scale of high end computing over the last decade, reliance on devices expressly designed for consumer electronics and commercial enterprise computing may impose severe limitations on future expansion of those same capabilities. Fortunately, exploration of innovations in parallel architecture and methods has revealed a plethora of advanced but practical strategies that aggressively attack these sources of performance degradation and may deliver future systems that efficiently perform a wide range of challenging algorithms while exhibiting a single system image across all name spaces. This one-hour presentation will diagnose the causes of current inefficiencies on conventional systems and describe the seminal innovations that are likely to circumvent their deficiencies. Included in this discussion will be such novel but near term concepts as streaming, field programmable logic, cell architecture, processor in memory, multithreading, parcel transaction processing, and latency tolerant programming, among others.