Reconfigurable logic devices, in particular FPGAs (Field Programmable Gate Arrays), have been successfully used in many embedded systems and for rapid prototyping for more than a decade. However, only the recent generations of FPGAs provide the gate density and the clock speed to make them really attractive for high performance parallel processing. Furthermore these chips are partially dynamically reconfigurable, i. e. they can change part of their configuration at runtime without interrupting processing in the rest of the chip. Hardcore and softcore processors as well as IP-cores for various applications also are supported. The talk reviews current approaches for reconfigurable logic and discusses their potentials and limits. As a case study for exploiting parallel processing with dynamically reconfigurable FPGAs, a coprocessor for network processors, DynaCORE, currently developed at the University of Luebeck for high-speed packet processing is presented in more detail.