Abstract
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This seminar will present work on the development of homogeneous multi-core chips based on the microthreaded model. It is important to note that the sequential machine/programming model is well understood and has served the computer industry well over the last half century, but it is now accepted that this situation is changing and even commodity systems, in the future, must be able to manage and exploit explicit concurrency. This means that the machine model must change. The goal of our work however, is to change the machine model but not the programming model.
At Amsterdam we have taken this constraint and adopted a concurrency model based on blocking threads that can be applied to all scales in a computing system, from instruction-level concurrency up to world- wide distributed applications. This scale free model is captured in the language µTC, which in turn can be implemented directly in microthreaded microprocessors (Dynamic RISC or DRISC processor). This model and its implementation has the following properties (advantages):
a) It is a dynamic model of concurrency that supports dynamic scheduling in its implementation, making translation from sequential languages much easier. It implements both fine-grain data synchronisation which is used to drive the dynamic instruction execution schedules as well as bulk synchronisation on families of related threads, giving synchronising reads and writes on data structures in asynchronous memory systems.
b) It uses concurrency as the basic composition mechanism for programs at all levels and sequence is captured only at the lowest levels, where static scheduling is deterministic (i.e. at the instruction level) or by means of explicit dependencies between threads (i.e. blocking threads).
c) The dependency patterns are constrained in order to allow concurrent composition without inducing communication deadlock, in order to expose locality of communication and in order to reason about resource issues in implementation. Dynamic resource allocation is mandatory in this model and hence resource deadlock becomes an issue. The constraint on communication allows the compiler to statically reason about resource issues, at least a sub-class of programs that do not have unbounded recursion in their composition.
The model provides all of the advantages of the sequential model while providing additional advantages of concurrent execution, which can be used for performance enhancement as well as power reduction. For example the model is deterministic, composition of programs in the model is safe, source code is universally compatible and finally binary code to a DRISC instruction set is forward compatible with systems comprising any number of such processors on a chip, i.e. we have binary code compatibility however many processors we use!
The model is also disruptive, so in our research we find ourselves investigating all issues related to computer systems, from ISA design to processor implementation and from compilers to operating systems. Currently we have a Microgrid multi-core simulator developed and are developing compiler from µTC to this ISA and from C to µTC, with the ultimate goal of being able to efficiently program multi-cores using the sequential paradigm.