The future growth and development of SoC technologies relies on the longer life cycle of the new chips in wireless communication and media processing. The current approach of integrating ASIC solutions is not economically attractive for the new generation of SoC chips, because of the NRE expenses (mask, engineering, validation, etc..) and shorter life cycle of the product. Therefore, a reprogrammable technology such as reconfigurable and highly parallel DSPs is the most cost effective approach that meets the real-time performance and power requirements of the next generation SoCs. Moreover, it provides a migration path across product generations meeting new standards and in-field upgrades. In this talk first I will present a taxonomy of the current RDSP techniques with emphasis on comparisons with ASIC solutions. The second part of the talk I will focus on a RDSP architecture and its applications, based on the Morpho Technologies IP core, and compare it with known competitors. Finally, I will give an overview of our research at UCI regarding parallel DSP architectures and applications.